1. Field of the Invention
The present invention is related to a shift register, and more particularly, to a shift register which drives pull-down circuits using low-frequency signals.
2. Description of the Prior Art
Liquid crystal display (LCD) devices, characterized in low radiation, small size and low power consumption, have gradually replaced traditional cathode ray tube (CRT) devices and been widely used in various electronic devices, such as notebook computers, personal digital assistants (PDAs), flat panel televisions or mobiles phones. Traditional LCD devices display images by driving the panel pixels using external driver chips. In order to reduce the number of devices and manufacturing costs, GOA (gate driver on array) technique has been developed in which the gate driver is directly manufactured on the LCD panel. A GOA gate driver usually functions in form of shift register, in which pull-up circuits provide a plurality of gate driving signals to the display panel and pull-down circuits stabilize output signals.
Referring to FIG. 1, which depicts a simplified functional diagram of a prior art LCD device 100. FIG. 1 only illustrates partial structure of the LCD device 100, including gate lines GL(1)-GL(N), a shift register 110, a clock generator 120 and a power supply 130. For operating the shift register 110, the clock generator 120 provides a start pulse signal VST and two high-frequency clock signals CH1 and CH2, while the power supply 130 provides bias voltages VDD and VSS. The shift register 110 includes a plurality of serially-coupled shift register units SR(1)-SR(N) having output ends coupled to corresponding gate lines GL(1)-GL(N), respectively. According to the high-frequency clock signals CH1, CH2 and the start pulse signal VST, the shift register 110 can sequentially output gate driving signals GS(1)-GS(N) to the corresponding gate lines GL(1)-GL(N) via the shift register units SR(1)-SR(N), respectively.
Referring to FIG. 2, which depicts a diagram of a shift register illustrated in U.S. Pat. No. 7,310,402 “GATE LINE DRIVERS FOR ACTIVE MATRIX DISPLAYS” (hereinafter as “prior art 1”). FIG. 2 illustrates a circuit diagram of an nth stage shift register unit SR(n) among the plurality of shift register units SR(1)-SR(N) in prior art 1 (n is an integer between 1 and N). The shift register unit SR(n) includes an input end IN(n), an output end OUT(n), a first pull-down circuit 16, a second pull-down circuit 26, a maintain circuit 36, a pull-up driving circuit 46, and a pull-up circuit 56. The input end IN(n) of the shift register unit SR(n) is coupled to the output end OUT(n−1) of the prior-stage shift register unit SR(n−1), while the output end OUT(n) of the shift register unit SR(n) is coupled to the input end IN(n+1) of the next-stage shift register unit SR(n+1). In prior art 1, the pull-up operation is performed by transistor switches T1 and T2, wherein the transistor switch T1 controls the signal transmission path between the input end IN(n) and the node Q(n) according to the gate driving signal GS(n−1), and the transistor switch T2 controls the signal transmission path between the clock signal CH1 and the output end OUT(n) according to the voltage level of the node Q(n). Meanwhile, the pull-down operation is performed by the first pull-down circuit 16 and the second pull-down circuit 26. In the first pull-down circuit 16, the serially-coupled transistor switches T3 and T4 respectively receive the high-frequency clock signals CH1 and CH2 having opposite phases at their respective gates, thereby generating control signals to the gates of the transistor switches T5 and T6. Therefore, the transistor switch T5 can control the signal transmission path between the node Q(n) and the voltage VSS according to its gate voltage, and the transistor switch T6 can control the signal transmission path between the output end OUT(n) and the voltage VSS according to its gate voltage. In the second pull-down circuit 26, the serially-coupled transistor switches T7 and T8 respectively receive the high-frequency clock signals CH2 and CH1 having opposite phases at their respective gates, thereby generating control signals to the gates of the transistor switches T9 and T10. Therefore, the transistor switch T9 can control the signal transmission path between the node Q(n) and the voltage VSS according to its gate voltage, and the transistor switch T10 can control the signal transmission path between the output end OUT(n) and the voltage VSS according to its gate voltage. The maintain circuit 36 maintains the gate voltages of the transistor switches T5, T6, T9 and T10 using the transistor switches T11-T13.
Referring to FIG. 3, which depicts a diagram of a shift register illustrated in U.S. Pat. No. 7,342,568 “SHIFT REGISTER CIRCUIT” (hereinafter as “prior art 2”). FIG. 3 illustrates a circuit diagram of an nth stage shift register unit SR(n) among the plurality of shift register units SR(1)-SR(N) in prior art 2 (n is an integer between 1 and N). The shift register unit SR(n) includes an input end IN(n), an output end OUT(n), a first pull-down circuit 18, a second pull-down circuit 28, a third pull-down circuit 38, a pull-up driving circuit 48, and a pull-up circuit 58. The input end IN(n) of the shift register unit SR(n) is coupled to the output end OUT(n−1) of the prior-stage shift register unit SR(n−1), while the output end OUT(n) of the shift register unit SR(n) is coupled to the input end IN(n+1) of the next-stage shift register unit SR(n+1). In prior art 2, the pull-up operation is performed by transistor switches T1 and T2, wherein the transistor switch T1 controls the signal transmission path between the input end IN(n) and the node Q(n) according to the gate driving signal GS(n−1), and the transistor switch T2 controls the signal transmission path between the clock signal CH1 and the output end OUT(n) according to the voltage level of the node Q(n). Meanwhile, the main pull-down operation is performed by the first pull-down circuit 18 and the second pull-down circuit 28. In the first pull-down circuit 18, the serially-coupled transistor switches T3 and T4 respectively receive the high-frequency clock signals CH1 and CH2 having opposite phases at their respective gates, thereby generating control signals to the gates of the transistor switches T5 and T6. Therefore, the transistor switch T5 can control the signal transmission path between the node Q(n) and the voltage VSS according to its gate voltage, and the transistor switch T6 can control the signal transmission path between the output end OUT(n) and the voltage VSS according to its gate voltage. In the second pull-down circuit 28, the serially-coupled transistor switches T7 and T8 respectively receive the high-frequency clock signals CH2 and CH1 having opposite phases at their respective gates, thereby generating control signals to the gates of the transistor switches T9 and T10. Therefore, the transistor switch T9 can control the signal transmission path between the node Q(n) and the voltage VSS according to its gate voltage, and the transistor switch T10 can control the signal transmission path between the output end OUT(n) and the voltage VSS according to its gate voltage.
Referring to FIG. 4, which depicts a timing diagram illustrating the operation of the prior art shift register. When driving the LCD devices in prior art 1 and prior art 2, the clock signals CH1 and CH2 switch between a high voltage level Vgh and a low voltage level Vgl based on a duty cycle of 50%, and have opposite phases at the same time. The 1st stage shift register unit SR(1) generates the 1st stage gate driving signal GS(1) according to the start pulse signal VST, while the 2nd-Nth stage shift register units SR(2)-SR(N) generate the 2nd-Nth stage gate driving signals GS(2)-GS(N) according to the output signals generated by their respective prior-stage shift register units. In other words, the gate driving signals GS(2)-GS(N) can be viewed as the start pulse signals which respectively enable the shift register units SR(2)-SR(N). The prior art shift register performs the pull-up operation between t1 and t3, and performs the pull-down operation after t3. For the nth stage shift register unit SR(n), the period between t1 and t2 is the driving period of its prior-stage shift register unit SR(n−1), during which the clock signal CH1 is at low voltage level, while the clock signal CH2 and the gate driving signal GS(n−1) are at high voltage level. The transistor switch T1 is thus turned on, thereby pulling up the node Q(n) to the high voltage level VDD. Meanwhile, the transistor switch T2 is also turned on, and the gate driving signal GS(n) is pulled down to the low voltage level Vgl due to the feed-through effect of the transistor switches in the pixels. At t2, the clock signal CH1 switches from low voltage level to high voltage level, thereby providing the gate driving signal GS(n) having high voltage level between t2 and t3 (when the clock signal CH1 is at high voltage level) via the turned-on transistor switch T2. On the other hand, the pull-down circuits 16, 26 and 18, 28 operate in a complimentary manner and each handles 50% of the pull-down operation. The gate driving signal GS(n) can thus be maintained at low voltage level VSS during the time excluding the driving period of the nth stage shift register unit SR(n). When the clock signal CH1 is at low voltage level, the clock signal CH2 is at high voltage level, the input signal of the shift register unit SR(n) (the gate driving signal GS(n−1)) is at low voltage level, and the output signal of the shift register unit SR(n) (the gate driving signal GS(n)) is at low voltage level, the gates of the transistor switches T5 and T6 are substantially kept at the low voltage level VSS, while the gates of the transistor switches T9 and T10 are substantially kept at the high voltage level VDD. Similarly, when the clock signal CH1 is at high voltage level, the clock signal CH2 is at low voltage level, and the output signal of the shift register unit SR(n) (the gate driving signal GS(n)) is at low voltage level, the gates of the transistor switches T5 and T6 are substantially kept at the high voltage level VDD, while the gates of the transistor switches T9 and T10 are substantially kept at the low voltage level VSS. Therefore, in the prior art shift register, the gates of the transistor switches T5, T6, T9 and T10 are kept at high voltage level for about 50% of a period, while at low voltage level for about 50% of the period.
With increasing demand for panel resolution, the charge time of the pixels is shortened. The clock signals CH1 and CH2 need to have higher frequencies, and power consumption also increases accordingly. In the prior art LCD devices, the high-frequency clock signals CH1 and CH2 are used for driving the pull-down circuits. In addition to high power consumption, the pull-down operation might eventually fail as the characteristics of the transistor switches deviate with time. Meanwhile, due to the feed-through effect, the gate driving signal GS(n) is discharged to the low voltage level Vgl which is lower than the ideal level VSS before its driving period, thereby causing charge coupling to the data voltages of the pixels and influencing the display quality of the LCD device.